FIG. 1 is a high level block diagram of a typical ATM switch. A switching fabric 100 capable of switching data packets from any to any of its switch input/outs is connected at least to a control unit 151 through leads 111 and 113 and to an adapter 102 through leads 103 and 105. There could be several other adapters, such as adapters 104 and 106, similar or identical to adapter 102. Each adapter is connected to the switching fabric through a pair of input/output leads, such as leads 101. The number of adapters which can be connected to the switching fabric is limited only by the number of available input/output leads.
Control element 151 controls the ATM switch, using a control processor 150, which may be a microprocessor. The control processor is connected to a DMA controller 152, which in turn is connected to a output buffer system 154 and an input buffer system 156. The primary function of the DMA controller 152 is to control the transfer of data between the buffer systems 154 and 156 and the control processor 150. The buffer system 154 is connected an ATM layer processing system 158. The buffer system is similarly connected to a second ATM layer processing system 160. The ATM layer processing systems perform normal ATM layer handling for ATM cells being switched between input and output ports through the switching fabric 100. Control RAMs 162, 164, 166 and 168 are used for storing control programs for the buffer system 154, the ATM layer processing system 158, the buffer system 156 and the ATM layer processing system 160, respectively.
One of the primary functions of adapter 102 is concentration of data received on the various adapter ports before ATM Transmission Convergence (TC) and layer functions are performed. The adapter includes a multiplexer circuit 110 for multiplexing ATM cells received on a set 130 of input ports P1 through P4. To accommodate different media that might be connected to the input ports, individual Physical Media Dependent (PMD) interface chips, such as chip 136, are interposed between the input ports and the multiplexer 110. The adapter further includes a demultiplexer 120 for demultiplexing or distributing ATM cells among ports in a set 131 of output ports. The demultiplexer 120 is connected through a second set of PMD interface chips, such as chip 137) which condition the outgoing data for the particular media attached to the output ports in set 131.
There are commercially available chips that perform the functions of chips 136 and 137. In the case of a 100 Mbps UNI (User-to-Network Interface), these chips can, for example, be Am7968/Am7969 TAXI chips from Advanced Micro Devices Corporation. In the case of a 155 Mbps UNI, these chips can be "framers"from NEC Corporation having a UTOPIA (standard) interface to the multiplexer 110 and demultiplexer 120.
The organization of adapter 102 is similar to the organization of the control element 151. Adapter 102 includes a first buffer system 112 for queueing data to be applied to the switching fabric 100, an associated ATM layer handling processor 116 and control memories 114 and 118 for the systems 112 and 116 respectively. The adapter further includes a second buffer system 122 for queueing data received from the switching fabric, as associated ATM layer handling processor 126 and control memories 124 and 128.
The described implementation of an ATM switch is intended to be illustrative only. Other implementations are possible, such as a system in which the control element and adapters are physically integrated onto the same or a few number of boards. Similarly, the switching fabric might be replaced by a switch or the functions might be allocated differently among the elements.
For further details on ATM concepts and techniques, reference may be had to the below-listed publications:
J. Y. LeBoudec, "The Asynchronous Transfer Mode: A tutorial", Comp Networks ISDN, 24, pp. 279-309, May 15, 1992. PA0 The ATM Forum, "UNI Specification", Version 3.0, Prentice Hall, ISBN 0-13-225863-3, September 1993, and Version 3.1, September 1994. PA0 The ATM Forum, "Interim Inter-Switch Signalling Protocol (IISP)", Draft 94-0924R2, November 1994. PA0 The ATM Forum, "P-NNI Draft Specification", Draft 94-0471 R3, 1994.
In known implementations, the Transmission Convergence functions are performed on a per-port basis; that is, there is a separate set of components for each port on an adapter. Standard Transmission Convergence functions, such as HEC (Header Error Correction) handling and maintenance of network management statistical counts are replicated on a port by port basis. The need for a dedicated set of components for each port clearly adds to the cost of the adapter and occupies physical space (or "real estate") on the adapter that might better be used for other purposes.
The current ATM UNI standard requires large network management statistical counters (thirty-two bits) in order to track the number of good received cells and the number of cells found to be in error after HEC checking. In known systems, two discrete thirty-two bit counters must be provided for each port. Since ATM switches typically have a large number of ports, the requirement for two counters per port adds considerable hardware to the switch.
One possible solution might be to use smaller counters (eight or twelve bit counters, for example) in the hardware elements with a larger counter in microcode supporting the hardware. The drawback of this approach is that performance can be impacted at the system level. To accurately maintain the counts in the microcode based counter, the microcode must read the two hardware counters assigned to each port often enough to avoid the possible of undetected hardware counter overflow. Thus if eight bit hardware counters were used to track good/bad cells, the microcode counter would have to read the hardware counters for each port at least every 2.sup.8 cell times.